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Freescale Semiconductor
Errata
MPC8260CE Rev. 4.6, 11/2004
MPC8260 PowerQUICC IITM Family Device Errata
This document describes all known silicon errata for the MPC8260 PowerQUICC IITM family of integrated communications processors. Refer to Table 3 for a list of devices. Table 1 lists new or modified errata.
Table 1. New Errata
Status New New Modified New New Item PCI14: PCI returns bad data on a master read following perr_response assertion. PCI15: Possible data corruption on PCI DMA writes with unaligned address.. CPM110: FCC1 Prioritization (Replaced Missing Description & Workaround) CPM120: SS7_OPT[FISU_PAD] parameter has no effect on the number of flags between FISUs. CPM121: Data frame may be corrupted if writing to xMR registers while other TDM channels are active. Page 21 21 52 57 57
Table 2 summarizes this document's revision history.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
Table 2. Document Revision History
Revision 4.5 Date 8/2004 Substantive Changes * Modified: CPM101: FCC RxClav timing violation (slave). * New Errata: CPM118: MCC Rx, Aborted HDLC frames. * New Errata: CPM119: FCC Tx, Incorrect handling of ethernet collision. * Modified: CPM101: FCC RxClav timing violation (slave). * Modified: CPM114: IDMA transfer has an extra DACKx. * New Errata: CPM117: False address compression. * New errata: G8 * New errata: CPM116 * New errata:CPM114, CPM115 * * * * New errata: PCI11-PCI12, CPM10-CPM113 Modified description of CPM57 Addition of HiP7 devices Addition of HiP4 rev C.0
4.4
4/2004
4.3 4.2 4.1 4
2/2004 12/2003 10/2003 9/2003
Prior to Revision 4
This document replaces three previous errata documents: * "MPC826x Family Device Errata" (MPC8260CE), Rev 3.1 * "XPC826xA Family Device Errata" (XPC8260ACE), Rev 1.3 * "MPC8260/XPC8260A Family Device Errata Summary" (MPC8260CESUMM), Rev 4.9
MPC8260 PowerQUICC II family devices are available in multiple silicon revisions, as shown in Table 3. To find which errata apply to a particular device, please refer to Table 4.
Table 3. MPC8260 Family Devices and Silicon Revisions
Silicon Process Device Revision Mask MPC8260(A) 1 MPC8250 2 MPC8255(A)1 MPC8264 MPC8265 MPC8266
1 2
0.29 m (HiP3) A.1 1K22A B.1 1K23A B.2 2K23A B.3 3K23A C.2 6K23A, 7K23A A.0 2K25A
0.25 m (HiP4) B.1 4K25A 2 2 C.0 5K25A
"A" designates HiP4 revisions of a device that was originally available in a HiP3 version. Also available in 516 PBGA (VR or ZQ) package in HiP4 Rev B.1 and Rev C.0 only.
Table 4 lists the silicon revisions to which each erratum applies and a reference to the page where each erratum is described.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 2 Freescale Semiconductor
Table 4. Errata Summary
.25 m (HiP4) Workaround A.1 B.1 B.2 B.3 C.2 A.0 B.1 C.0 exists SIU SIU1 SIU2 SIU4 SIU5 SIU6 SIU8 SIU9 SIU10 SIU12 SIU13 SIU14 SIU16 SIU17 SIU18 SIU19 -- Yes Yes Yes -- -- Yes Yes Yes -- Yes Yes Yes -- Yes Wrong timer advancement on RCCR. DMA error upon assertion of ARTRY. Incorrect masking of MCP. Incorrect report of TEA. Software watchdog reports soft reset. Parity when bus port size is less than 64 bit. The bus monitor erroneously asserts TEA after ARTRY. 7 7 8 8 8 9 9 .29 m (HiP3)
Errata
Description
Page
Strict enforcement of requirement to assert DBG and TS 10 In the same cycle when core enabled. In the core disabled mode, CPU_BR_B powers up in a random state. SDAMUX not valid in single MPC8260 mode. Errata in parity operation when BRx[DR] = 1. Bus busy disable mode. Bus error causes TEA to asserted twice. ARTRY assertion when using pipeline depth of 0. Bus monitor time-out when using external slave. General 10 11 11 11 12 13 13
G1 G3 G4 G8

-- Yes Yes --
Incorrect AC timings: outputs switch later than specified. 14 PLL does not lock on the rising edge of the input clock CLKIN. 14
Incorrect AC timings: outputs switch later than specified. 15 Assert PORESET to ensure correct JTAG operation. PCI 15
PCI1 PCI2 PCI3 PCI4 PCI5 PCI6 PCI7

Yes Yes -- --
PCI DMA operation after bus error. PCI I2O operation. PCI configuration registers, class code. PCI TVAL hold time. PCI does not negate ARTRY properly. CPM frequency limitation in non-integer bus-to-CPM clock ratios in PCI mode.
16 16 16 17 17 18

Yes -- Yes
Access to PCI memory-mapped configuration registers in 18 non-PCI mode.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 3
Table 4. Errata Summary (continued)
.25 m (HiP4) Workaround A.1 B.1 B.2 B.3 C.2 A.0 B.1 C.0 exists Yes Yes Yes -- .29 m (HiP3)
Errata PCI8 PCI9 PCI11 PCI12
Description Output bus clock in PCI agent mode. Simultaneous PCI inbound write transactions and PCI outbound read transactions can cause bus deadlock. Outbound translation window can overlap PCI memory-mapped configuration space.
Page 18 19 20
Deassertion of GNT# during the address stepping cycle 20 of an outbound configuration write transaction can cause PCI bus to hang. PCI returns bad data on a master read following perr_response assertion. Possible data corruption on PCI DMA writes with unaligned address. CPU 21 21
PCI14 PCI15

Yes Yes
CPU1
--
Error in MCP reporting. CPM
22
CPM1 CPM2 CPM4 CPM5 CPM6 CPM7 CPM8 CPM9 CPM10 CPM11 CPM13 CPM14 CPM15 CPM17 CPM18 CPM21 CPM22 CPM23 CPM24 CPM27

-- -- -- -- -- -- Yes Yes -- -- -- Yes Yes -- Yes Yes -- Yes -- --
Erroneous LG error indication in MCC. CAM access not atomic. No CTS lost indication with HDLC. Data corruption on DMA fly-by. Erroneous report of overrun on FCC. Erroneous report of overrun with Fast Ethernet. Error using FCC transmit on demand register. Erroneous reception of ATM cell. Error in ATM underrun report. False indication of shared flag. Error in random number generation. Corruption of ATM cells using AAL1 and UDC. Corruption of Port D registers. Error in reporting UTOPIA error condition. Error in UTOPIA slave transmit mode. False indication of collision in Fast Ethernet. False defer indication in Fast Ethernet. Corruption of AAL5 header. Error in indicating IDLE between frame. Error in heartbeat checking in FCC.
22 23 23 23 24 24 25 25 25 26 26 27 27 27 28 28 29 29 29 30
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 4 Freescale Semiconductor
Table 4. Errata Summary (continued)
.25 m (HiP4) Workaround A.1 B.1 B.2 B.3 C.2 A.0 B.1 C.0 exists Yes -- -- Yes Yes -- Yes Yes Yes Yes Yes Yes Yes -- -- Yes Yes Yes Yes Yes -- Yes -- Yes Yes Yes Yes Yes Yes -- Yes .29 m (HiP3)
Errata CPM28 CPM29 CPM30 CPM35 CPM36 CPM38 CPM39 CPM40 CPM41 CPM42 CPM43 CPM44 CPM45 CPM46 CPM47 CPM48 CPM49 CPM50 CPM51 CPM52 CPM53 CPM54 CPM55 CPM56 CPM57 CPM62 CPM64 CPM65 CPM71 CPM72 CPM73
Description Error in receive frame threshold. MAXD1 and MAXD2 may not be less than MFLR. Graceful stop command does not work. Data corruption in SCC transparent mode. SI sync timing restriction. Heart beat error and carrier sense lost error on two frames. Corruption in AAL0 cell payload. Corruption in AAL0 IDLE Cell. Limitation in ATM controller. Data corruption in MCC. TxCLAV ignored by UTOPIA in single PHY mode. Zero insertion error on MCC. Error in CLAV sample point. Error in internal prioritization of CPM resource.
Page 30 30 31 31 32 32 33 33 33 34 34 35 35 35
Error in tri-state ability of two TxDATA signals using 16-bit 36 UTOPIA interface on FCC1. Error in TDM. Error in FEC CAM address recognition. Error in loss of alignment. Pointer insertion/extraction error in AAL1 CES. Error in ATM internal rate mode. Inability to run RAM microcode. Error in switching to and from shadow SI RAM. Error in ATM_Transmit command. AAL2 microcode in ROM does not function. AAL5 cell corruption. The CPM PLL does not lock reliably for certain multiplication factors. 36 37 37 38 38 38 39 39 40 40 41
AAL5 RxBD[LNE] error generated if PDU length exceeds 41 65512 bytes. SS7 microcode in ROM is not fully functional. CPM does not snoop MCC buffer descriptors. MCC global underruns. SIRAM corruption. 41 42 42 43
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 5
Table 4. Errata Summary (continued)
.25 m (HiP4) Workaround A.1 B.1 B.2 B.3 C.2 A.0 B.1 C.0 exists Yes Yes -- -- Yes Yes -- Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -- Yes Yes Yes Yes Yes Yes .29 m (HiP3)
Errata CPM75 CPM77 CPM78 CPM79 CPM80 CPM81 CPM85 CPM86 CPM88 CPM92 CPM93 CPM94 CPM95 CPM96 CPM97 CPM98 CPM99 CPM100 CPM101 CPM110 CPM111 CPM112 CPM113 CPM114 CPM115 CPM116 CPM117 CPM118 CPM119
Description AAL2 microcode in ROM is not fully functional.
Page 43
TC layer transmits and receives data LSB first instead of 44 MSB first. IMA microcode in ROM is not fully functional. FCC Fast Ethernet flow control. MCC CES user template. Japanese SS7 error interval timer problem. AAL0 only one BSY interrupt generated. 44 44 45 45 46
Random PHY number for FCC Rx in Single-PHY master 46 mode. MCC transmit GUN when `MCC STOP RX' CPCR command is used. TC Layer when disabled can be selected by FCC2. IDMA microcode in ROM is not fully functional. FCC RTS signal not asserted correctly. ATM false indication of miss inserted cells. ATM performance monitoring with AAL1 CES. MCC SS7--No SUERM interrupt generated after an ABORT. I2C erratic behavior can occur if extra clock pulse is detected on SCL. ABR TCTE[ER-TA] corruption. ABR TCTE address miscalculation. FCC RxClav timing violation (slave). FCC1 prioritization. FCC missing reset at overrun. FCC missing status. 46 47 48 48 48 49 49 50 50 51 51 52 53 53
Incorrect return value from event register read (SCC, SPI, 54 I2C, and SMC). IDMA transfer has an extra DACKx. APC transmits unwanted idle cells. 54 55
The pointer value of 93 is not supported in PFM mode of 55 AAL1 CES. False address compression. MCC Rx, Aborted HDLC frames. FCC Tx, Incorrect handling of ethernet collision. 56 56 57
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 6 Freescale Semiconductor
Table 4. Errata Summary (continued)
.25 m (HiP4) Workaround A.1 B.1 B.2 B.3 C.2 A.0 B.1 C.0 exists Yes Yes .29 m (HiP3)
Errata CPM120 CPM121
Description SS7_OPT[FISU_PAD] parameter has no effect on the number of flags between FISUs. Data frame may be corrupted if writing to xMR registers while other TDM channels are active.
Page 57 57
Part I System Interface Unit (SIU) Errata
SIU1:
Devices: MPC8260, MPC8255 Description: The MPC8260 treats the RCCR[TIMEP] value (UC timer) differently than QUICC. In QUICC, the timer advanced (N+1)*1024 cycles and in XPC8260 the timer advances N*1024 cycles. Workaround: -- Fix Plan: Fix on HiP3 B.1
Wrong timer advancement on RCCR.
SIU2:
Devices:
DMA error upon assertion of ARTRY.
MPC8260, MPC8255 Description: Address retry assertion by a bus master on the 60x bus may confuse XPC8260's DMA. Examples of external masters that use address retry are PCI bridge processor, which uses cache in copy-back mode, and some ASICS Workarounds: * * * * Place XPC8260 in single 8260 bus mode. Work with external L2 cache in write-through mode. Inhibit external PCI bridge from using address retry Design ASIC interface not to use address retry
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 7
If an external PCI bridge exists and it has the capability to drive ARTRY, only the CPM DMA must be allowed to perform accesses through the PCI bridge after the CPM has been activated (that is, no core accesses through the PCI bridge after this point). Fix Plan: Fix on HiP3 B.1
SIU4:
Devices:
Incorrect masking of MCP.
MPC8260, MPC8255 Description: MCP (machine check interrupt) due to data errors (parity/ECC) is masked by the SWRI bit in SYPCR. Workaround: Clear the SWRI bit in SYPCR to get data error indication. Fix Plan: Fix on HiP3 B.1
SIU5:
Devices:
Incorrect report of TEA.
MPC8260, MPC8255 Description: Data parity error in the local bus does not cause MCP interrupt. Workaround: Use TEA for parity error in local bus by setting bit 16 of L_TESCR1. Fix Plan: Fix on HiP3 B.1
SIU6:
Devices:
Software watchdog reports soft reset.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 8 Freescale Semiconductor
Description: The events from software watchdog and bus monitor should cause assertion of hard reset. Currently, these events cause assertion of soft reset. Workaround: -- Fix Plan: Fix on HiP3 B.1
SIU8:
Devices:
Parity when bus port size is less than 64 bit.
MPC8260, MPC8255 Description: When reading from a device with a port size of less than 64 bits, from an address not aligned to 64 bits, the parity bits for parity check are not taken from the write locations (for example, for a read of 4 bytes from a 32-bit port size from address 4, the parity is checked against dp[4:7] when it should be checked against dp[0:3]). The bug exists for both normal and RMW parity, and for both the 60x and local buses. Workaround: -- Fix Plan: Fix on HiP4 A.0
SIU9:
Devices:
The bus monitor erroneously asserts TEA after ARTRY.
MPC8260, MPC8255 Description: The bus monitor will assert TEA if a bus cycle does not complete in a certain amount of time. In case there is an ARTRY cycle, the bus monitor will not recognize the complication of the transaction and will assert TEA if there is no bus activity following the TEA for a time equal to the bus monitor time-out. Workaround: Disable the bus monitor in system where ARTRY cycles are used, for example, systems were external PCI bridge chip is used.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 9
Fix Plan: Fix on HiP3 C.2
SIU10:
Devices:
Strict enforcement of requirement to assert DBG and TS in the same cycle when core enabled.
MPC8260, MPC8255 Description: In systems where the XPC8260 core is enabled, an external arbiter must assert DBG in the same clock in which TS is asserted (there may be a one-clock delay in the PPC_ACR[DBGD] bit is set; however out of reset this bit is not set by default). Some external arbiters, including the one implemented in Tundra PowerSpan device, do not meet this requirement. As a result, the system gets stuck following the first bus access after reset. In XPC8260 Rev A.1 silicon this condition was relaxed and DBG could be asserted one clock later. However in XPC8260 Rev B.X silicon, this requirement is strictly enforced, and some systems that include external arbiters that worked with Rev A.1 silicon will not work with Rev B.X Workaround: Do not use the external arbiter with Rev B.X silicon, which does not meet the above requirement to assert DBG and TS in the same cycle, or, alternatively, use the internal MPC8260 bus arbiter. Fix Plan: Fix on HiP3 C.2
SIU12:
Devices:
In the core disabled mode, CPU_BR_B powers up in a random state.
MPC8260, MPC8255 Description: When the core is disabled, the CPU_BR_B (bus request by the 603 core) powers up in random state. If it happens to power-up asserted it will request the bus all the time, and the internal arbiter will be deadlocked, disregarding the bus requests from the external devices. As a result, the system does not start fetching instructions after reset. Workaround: Set the MMR field in the hard reset configuration word (HRCW) to 0b10. This will mask the core bus request and allow the bus to be granted to external master 1. As a side effect it will also mask the bus requests from the external masters 2 and 3. The SIUMCR[MMR] field must not be changed after power-on reset. The bus requests issued by the CPM (that is, SDMA) will not be masked.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 10 Freescale Semiconductor
Fix Plan: Fix on HiP3 C.2
SIU13:
Devices:
SDAMUX not valid in single MPC8260 mode.
MPC8260, MPC8255 Description: SDAMUX signal is disabled (stuck at '0') when SDRAM machine handles the memory access and the chip is programmed to single MPC8260 mode (BCR[EBM] = 0). Workaround: -- Fix Plan: Fix on HiP3 C.2
SIU14:
Devices:
Errata in parity operation when BRx[DR] = 1.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When reading from a device with port size less then 64 bit, parity checking is not performed at the right location when BRx[DR] = 1, and parity errors will result. This problem exists for both normal and RMW parity, and for both the 60x and local buses. Workaround: Use BRx[DR] = 0 for no data pipelining. Fix Plan: Fix on HiP4 B.1
SIU16:
Devices:
Bus busy disable mode.
MPC8260, MPC8255, MPC8260A, MPC8255A,MPC8250, MPC8264, MPC8265, MPC8266
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 11
Description: Bus busy disable mode (SIUMCR[BBD = 1]) cannot be used if the 826x or the 826xA is not the only master on the 60X bus. Using this mode in such a system can cause the 60X bus to hang. Workarounds: 1. If the external master supports the ABB signal, do not use bus busy disable mode and connect this signal to the 826x or the 826xA. The DBB signal can either be connected or can be pulled up. 2. If the external master doesn't support the ABB signal, do one of the following: -- Do not use bus busy disable mode and generate the ABB signal externally. The DBB signal can either be connected or can be pulled up. The following external ABB implementation should be enough to work around the problem: assert the ABB signal whenever a qualified bus grant for the external master is sampled (bus grant asserted while ARTRY and ABB are negated). Negate the ABB signal when there is no qualified bus grant. The negation of ABB should be as follows: drive ABB to VDD for half a clock cycle and then stop driving it (HIGH-Z). -- If using the internal arbiter and up to two external masters, connect the external bus grants (through an AND gate if more than one) to an available external bus request and define the priority for that request to be the highest in the PPC_ALRH register. The DBB signal can either be connected or can be pulled up. Note that workaround 2 should be implemented only for external masters that do not support ABB. If some of the masters support ABB and another masters do not, then the masters that do support it should simply connect the ABB signal to the PQ2. Fix Plan: No fix plan at this time.
SIU17:
Devices:
Bus error causes TEA to asserted twice.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When the local bus is accessed through the 60x bus, this single transaction turns on both local bus and 60x bus monitors. If there is bus error, then TEA will be asserted twice a few cycles apart. If the 826x initiates this transaction, then TEA being asserted twice will result in the CPU entering a checkstop state. Workaround: Disable 60x bus monitor, SYPCR[PBME] = 0. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 12 Freescale Semiconductor
SIU18:
Devices:
ARTRY assertion when using pipeline depth of 0.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: Internal (60x) slave maintains a pipeline depth of zero by asserting AACK only after TA. When ARTRY is asserted the 60x bus access will be terminated and TA will not be asserted. Therefore, the internal (60x) slave will not assert AACK, since TA was not asserted. Workaround: Use a pipeline depth of one (BCR[PLDP] = 0) for applications that require memory coherency. Fix Plan: No fix plan at this time.
SIU19:
Devices:
Bus monitor time-out when using external slave.
MPC8260, MPC8255, MPC8260A, MPC8255A,MPC8250, MPC8264, MPC8265, MPC8266 Description: When using an external 60x bus slave with the bus monitor activated. PSDVAL is not asserted when the external slave is accessed, which could cause the bus monitor to time-out and TEA to be asserted. Workarounds: 1. Use pipeline depth of zero (BCR[PLDP] = 1) when using an external 60x bus slave 2. Disable 60x bus monitor, SYPCR[PBME] = 0 3. If the external 60x bus slave is another 826x device, connect the PSDVAL signals together Fix Plan: --
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 13
Part II General Errata
G1:
Devices: MPC8260, MPC8255 Description: The maximum output delay defined by sp32 is 10 ns. The specification is 8 ns. The maximum output delay defined by sp35 is 7.5 ns. The specification is 7 ns. The maximum output delay defined by sp36a is 6.5 ns. The specification is 6 ns. Workaround: -- Fix Plan: Fix on HiP3 C.2
Incorrect AC timings: outputs switch later than specified.
G3:
Devices:
PLL does not lock on the rising edge of the input clock CLKIN.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266
Description: In correct operation, the PLL of the MPC826x devices will lock on the rising edge of the input clock. However, on the MPC826xA (Hip4) silicon, the PLL locks on the falling edge of the input clock if an integer CPM multiplication factor is used. This will affect the skew between CLKIN and internal clock at the rising edge since the skew is dependent on the duty cycle of the input clock. This will affect synchronous designs where the same clock source is used as an input to CLKIN as well as to an external synchronous device (for example, a peripheral or ASIC). The MPC826xA internal logic assumes that the internal clock's rising edge will be in sync with CLKIN. Workaround: Use a non-integer CPM multiplication factor. This workaround does not apply to PCI agent mode, since the multiplication factor in PCI agent mode must be an integer.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 14 Freescale Semiconductor
NOTE Please note that in PCI agent mode, since the clock provided by the user is the PCI clock, the skew due to non-50% duty cycle will be seen between the PCI clock and the internal clock. The bus clock in this case is supplied by the 8260, and if the clk2 skew elimination function is used, then the internal clock will be in phase with the bus clock. Fix Plan: Fix on HiP4 B.1
G4:
Devices:
Incorrect AC timings: outputs switch later than specified.
MPC8260, MPC8255
Description: The maximum output delay defined by sp34 is 11 ns. The specification is 6 ns. Workaround: Set P/LSDMR [BUFCMD] = 1 or set P/LSDMR [EAMUX] = 1. Fix Plan: Fix on HiP3 B.1
G8:
Devices:
Assert PORESET to ensure correct JTAG operation.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266
Description: To ensure correct operation of the JTAG module, it is required to assert the PORESET external pin at least once after the processor is powered up, for the duration of at least 240 ns, even though the clock input for the CLKIN is not required. Without asserting PORESET at least once, an internal test feature might randomly awaken and disable JTAG BSR testability. PORESET should be negated before starting JTAG operations. Workaround: -- Fix Plan: --
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 15
Part III PCI Errata
PCI1:
Devices: MPC8250, MPC8265, MPC8266 Description: The PCI DMA may lock up if it attempts to perform a DMA cycle following a cycle that was terminated by a bus error. Workaround: On a PCI-enabled system, one must reset the system if a bus error is detected. Fix Plan: No fix plan at this time.
PCI DMA operation after bus error.
PCI2:
Devices:
PCI I2O operation.
MPC8250, MPC8265, MPC8266 Description: When the conditions for the outbound post queue interrupt assertion are valid, and OMIMR[OPQIM] is set, OMISR[OPQI] is cleared. Workaround: Do not read the state of OMISR[OPQI] when OMIMR[OPQIM] is set. Fix Plan: No fix plan at this time.
PCI3:
Devices:
PCI configuration registers, class code.
MPC8250, MPC8265, MPC8266 Description: When configured as a PCI agent device, the value of the base class code, subclass and interface registers are 0x0e, 0x00 and 0x01 respectively, indicating that it supports the I2O protocol. Since the I2O support is not fully compliant, future revisions of the MPC826x will not use this value in the class code fields.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 16 Freescale Semiconductor
Workaround: -- Fix Plan: No fix plan at this time.
PCI4:
Devices:
PCI TVAL hold time.
MPC8250, MPC8265, MPC8266 Description: PCI bridge only supports 1-ns hold time for Tval. Tval is a timing spec listed in the PCI-SIG that specifies CLK to signal valid. To support 33 MHz the minimum must be 2 ns. Workaround: -- Fix Plan: Fix on HiP4 B.1
PCI5:
Devices:
PCI does not negate ARTRY properly.
MPC8250, MPC8265, MPC8266 Description: For normal recommended pull-up resistor (10 K), ARTRY is negated 2 cycles after AACK assertion instead of one. Under certain PCI traffic patterns, this extra cycle ARTRY assertion could lead to 60x bus deadlock. Workaround: Use a 300- pull-up resistor on ARTRY Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 17
PCI6:
Devices:
CPM frequency limitation in non-integer bus-to-CPM clock ratios in PCI mode.
MPC8250, MPC8265, MPC8266 Description: In PCI mode (agent or host), when the clock ratio between bus clock and CPM clock is not an integer ratio (1:2.5, 1:3.5) the frequency of the CPM is limited to 166 MHz. Workaround: -- Fix Plan: No fix plan at this time.
PCI7:
Devices:
Access to PCI memory-mapped configuration registers in non-PCI mode.
MPC8250, MPC8265, MPC8266 Description: In non-PCI mode, the internal memory space (DPRAM, registers and the local bus bridge) will not be accessible any more after an access to the PCI memory-mapped configuration registers area (offsets 10400-10BFF). The access to the above area and any following access to the internal memory space will not be terminated normally and can only be terminated by TEA if the 60x bus monitor is activated. The system can recover only after a soft reset. Workaround: In non-PCI mode, do not access the described area. Note that this area is reserved in non-PCI mode. Fix Plan: No fix plan at this time.
PCI8:
Devices:
Output bus clock in PCI agent mode.
MPC8250, MPC8265, MPC8266
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 18 Freescale Semiconductor
Description: In PCI agent mode, the DLL output reference clock is used externally as the bus clock. If the CPM/BUS ratio is non-integer (2.5 and 3.5), the output bus clock from the DLL will not have a 50% duty cycle. Instead the output bus clock will have a duty cycle of: 2.5 -- 40% or 60% 3.5 -- 43% or 57% Workaround: In hardware add a zero delay buffer to the DLLOUT signal. Fix Plan: No fix plan at this time.
PCI9:
Devices:
Simultaneous PCI inbound write transactions and PCI outbound read transactions can cause bus deadlock.
MPC8250, MPC8265, MPC8266 Description: In PCI mode, when both outbound and inbound traffic happens simultaneously, it is possible that after some random number of transactions the system will hang. The deadlock situation might be caused by one of the following events: -- 60x master reads from PCI memory/IO/config space while a PCI master writes into 60x memory, or -- 60x master reads from PCI memory/IO/config space while a PCI bridge's DMA channel writes into 60x memory, or -- 60x master reads from PCI bridge's internal register while a PCI master writes into 60x memory, or -- 60x master reads from PCI bridge's internal register while a PCI bridge's DMA channel writes into 60x memory. Workaround: Do not allow simultaneous outbound read and inbound write transactions, or use IDMA mechanism to perform data read from PCI memory/IO/config space and from PCI bridge's internal registers. Also note that the IDMA should be initialized in such a way that the source (PCI memory/IO/config space/ PCI bridge's internal registers) should be selected to locate on local bus in the IDMA BD (SDTB = 1). Fix Plan: Fix on HiP4 C.0
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 19
PCI11:
Devices:
Outbound translation window can overlap PCI memory-mapped configuration space.
MPC8250, MPC8265, MPC8266 Description: If an outbound translation window is programmed to have a translation that maps an address to any of the following addresses: IMMR+0x10900, IMMR+0x10904, or IMMR+0x10908, a memory transaction will not be generated on PCI. Instead the PCI CFG_ADDR, PCI CFG_DATA, or PCI INT_ACK registers of the memory mapped configuration space will be accessed. Workaround: Do not allow software to program the Outbound Translation Window such that it maps an address to IMMR+10900, IMMR+10904, IMMR+10908. To make this more general, software can be restricted so an Outbound Translation Window can not overlap the Internal Memory Map Configuration window. Fix Plan: No fix plan at this time.
PCI12:
Deassertion of GNT# during the address stepping cycle of an outbound configuration write transaction can cause PCI bus to hang.
Devices: MPC8250, MPC8265, MPC8266 Description: A configuration write transaction is mastered by the IOU and this transaction is retried. The configuration write transaction is then mastered again on the PCI bus. If during the address stepping cycle of the configuration transaction (the cycle before FRAME# is asserted) the IOU GNT# signal is deasserted, the PCI bus can hang. The PCI bus can potentially hang if configuration write transactions are retried in host mode and other masters are requesting the PCI bus. In agent mode the IOU will not be mastering configuration transactions so there shouldn't be any problems. A configuration write transaction is mastered by the IOU and this transaction is retried. The configuration write transaction is then mastered again on the PCI bus. If during the address stepping cycle of the configuration transaction (the cycle before FRAME# is asserted) the IOU GNT# signal is deasserted, the PCI bus can hang. The IOU GNT# signal is provided either by the internal or by the external arbiter, depending on arbiter configuration. The hang on the PCI bus manifests itself by FRAME# being asserted without the assertion of IRDY# indefinitely or no assertion of FRAME# at all.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 20 Freescale Semiconductor
Workaround: -- Fix Plan: No fix plan at this time.
PCI14:
Devices:
PCI returns bad data on a master read following perr_response assertion.
MPC8250, MPC8265, MPC8266 Description: If the value of the PERR bit of the PCI Bus Command Register (0x04 in the configuration space) is changed from 0 to 1 by using the CFG_DATA register and if there is a master read immediately following, the wrong read data is returned to the IOS. Workaround: 1. Unless the core is fetching its instructions from the PCI space, writing to the register twice or writing and then reading it, prevents the problematic case from occurring. 2. Do not use clock ratios above 6:1. Fix Plan: No fix plan at this time.
PCI15:
Devices:
Possible data corruption on PCI DMA writes with unaligned address.
MPC8250, MPC8265, MPC8266 Description: If the PCI DMA destination address is in the 60x space and the data transfers are not multiples of 8 bytes and/or are not aligned to 8 bytes, the DMA might generate multi-beat write transactions with invalid bytes. As a result, the PCM generates a 60x transaction that writes beyond the allocated buffer. The PCM may also get stuck. Workaround: When transferring data to the 60x space using PCI DMA, use only destination address and byte counts that are multiples of 8.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 21
Fix Plan: No fix plan at this time.
Part IV Core Processing Unit (CPU) Errata
CPU1:
Devices: MPC8260, MPC8255 Description: Errors that cause MCP assertion are not reported in any status register. When MCP is asserted the CPU will branch to bus error vector (0x200) but it is not possible to know the cause of the error. Data errors including data parity and ECC are also reported by MCP assertion. Workaround: -- Fix Plan: Fix on HiP4 B.1
Error in MCP reporting.
Part V Communications Processor Module (CPM) Errata
CPM1:
Devices: MPC8260, MPC8255 Description: In MCC HDLC when MFLR is a multiple of 8 and the frame length is exactly MFLR there might be LG error indication and interrupt on this frame. Workaround: --
Erroneous LG error indication in MCC.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 22 Freescale Semiconductor
Fix Plan: Fix on HiP3 B.1
CPM2:
Devices:
CAM access not atomic.
MPC8260, MPC8255 Description: The bus tonicity mechanism for CAM access may not function correctly when the CPM's DMA accesses the CAM. This only affects systems in which multiple CPM's will access the CAM. Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM4:
Devices:
No CTS lost indication with HDLC.
MPC8260, MPC8255 Description: When CTS is negated at the end of HDLC frame, (last flag or one byte before) transmission will be aborted, however there will be no CTS-lost indication. There will be only an abort indication. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM5:
Devices:
Data corruption on DMA fly-by.
MPC8260, MPC8255 Description: The data of a DMA write, which follows a DMA fly-by read in the local bus, may be corrupted.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 23
Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM6:
Devices:
Erroneous report of overrun on FCC.
MPC8260, MPC8255 Description: Spurious overrun indications on the FCC may occur in the following cases: -- After issuing stop transmit command. -- Following CTS lost condition. -- Late collision under Ethernet. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM7:
Devices:
Erroneous report of overrun with Fast Ethernet.
MPC8260, MPC8255 Description: In case the CRS (carrier sense) signal is negated while fast Ethernet frame is transmitted, an overrun error might occur and the FCC may have to be reset. Workaround: -- Fix Plan: Fix on HiP4 A.0
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 24 Freescale Semiconductor
CPM8:
Devices:
Error using FCC transmit on demand register.
MPC8260, MPC8255 Description: The TODR mechanism may freeze an FCC serial channels. Workaround: For an FCC do not use the TODR. Fix Plan: Fix on HiP4 A.0
CPM9:
Devices:
Erroneous reception of ATM cell.
MPC8260, MPC8255 Description: Under certain condition ATM receiver may receive cells of PHYs that were not addressed for it. Details of the condition: -- ATM receiver in UTOPIA slave mode. -- FIFO full condition occurred (this will happen only when the transmitter violates -- the UTOPIA standard requirements: transmits data without CLAV). -- Transmitter changed selected PHY number. -- FIFO full condition ended (CPM read some data from FIFO). Workaround: Use different VPI/VCI for different PHYs or expect the cells to be discarded by higher level protocol software. Fix Plan: Fix on HiP4 A.0
CPM10:
Devices:
Error in ATM underrun report.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 25
Description: In ATM, Transmit internal rate underrun error is not reported correctly in TIRU in FCCE register. In most cases TIRU will not be set in FCCE when internal rate underrun error occurs. In some rare cases that depend on internal sequences within the communication controller, the TIRU bit might be set as expected when the error should be reported. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM11:
Devices:
False indication of shared flag.
MPC8260, MPC8255 Description: FCC-TX HDLC - FCT_TXD (data out) changes from 1-->0 for 1 ser_clock period, few clocks after reset command from MAIN is given. A false shared flag can be detected at the receiver, if last bit before reset was 0, and the receiver will consider it as a closing flag of the frame. In most of cases a CRC error will be generated and the frame will be discarded. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM13:
Devices:
Error in random number generation.
MPC8260, MPC8255 Description: In Fast Ethernet transmit, when more than one (up to four) frames reside in the FCC FIFO, random number generation (for collision wait) may produce the same number for all four frames. Workaround: --
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 26 Freescale Semiconductor
Fix Plan: Fix on HiP4 A.0
CPM14:
Devices:
Corruption of ATM cells using AAL1 and UDC.
MPC8260, MPC8255 Description: Corruption of ATM cells may occur when using the following combination: AAL1 with UDC in which the user defined header size is 9 to 12 octets and PM is not used. Workaround: Since this problem appears in a very specific condition as described above, avoiding any of the elements (e.g. use cell header of 8 octets) will eliminate it. Fix Plan: Fix on HiP3 B.1
CPM15:
Devices:
Corruption of Port D registers.
MPC8260, MPC8255 Description: The PDATA, PDATB, PDATC, and PDATD registers can only be written with 32 bit write instruction. (that is, store word stw) When using 8- or 16-bit write instruction (that is, store half word sth, or store byte stb instructions), the bits not being written to may be corrupted. Workaround: Use 32-bit write instruction only to write to PDATA, PDATB, PDATC, and PDATD registers. Fix Plan: Fix on HiP3 B.1
CPM17:
Devices:
Error in reporting UTOPIA error condition.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 27
Description: The FCC receiver, which is configured as single PHY master, does not detect UTOPIA error condition when SOC and CLAV are not asserted simultaneously. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM18:
Devices:
Error in UTOPIA slave transmit mode.
MPC8260, MPC8255 Description: When the XPC8260 is configured to work as UTOPIA slave device in multi slave PHY mode, and the TXEN input signal is asserted constantly, the XPC8260 will transmit one cell and transmission will stop. Workaround: Ensure that TXEN is negated whenever the TXCLAV is negated. Fix Plan: Fix on HiP4 A.0
CPM21:
Devices:
False indication of collision in Fast Ethernet.
MPC8260, MPC8255 Description: In the Fast Ethernet a false COL will be reported whenever a collision occurs on the preamble of the previous frame. Workaround: Software should ignore COL indications when the CRC of the frame is correct. Fix Plan: Fix on HiP4 A.0
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 28 Freescale Semiconductor
CPM22:
Devices:
False defer indication in Fast Ethernet.
MPC8260, MPC8255 Description: In the fast Ethernet if a frame was transmitted due to defer and this frame also got late collision, a false defer indication will be indicated for the next frame. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM23:
Devices:
Corruption of AAL5 header.
MPC8260, MPC8255 Description: When working in AAL5 user defined cell mode and CPCS_UU is disabled, the UDC header may be corrupted. Workaround: When working with AAL5 UDC, use CPCS enabled mode. Fix Plan: Fix on HiP3 B.3
CPM24:
Devices:
Error in indicating IDLE between frame.
MPC8260, MPC8255 Description: In FCC HDLC transmitter if slow serial clock (CPM _freq/serial_clock > 16) is used RTS will not transition to IDLE between frames. This means that all the frames will be transmitted back to back in case there is valid data in the transmitter's FIFO. Workaround: --
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 29
Fix Plan: Fix on HiP4 A.0
CPM27:
Devices:
Error in heartbeat checking in FCC.
MPC8260, MPC8255 Description: The heartbeat checking in FCC transmit Ethernet 10Mbps does not work properly. The standard requires that the collision pulse from the PHY should be checked within a window of 4usec from the falling edge of the carrier sense. The XPC8260 samples the collision signal only once at exactly 4usec (10 serial clocks) after the falling edge of the carrier sense signal. Workaround: -- Fix Plan: Fix on HiP4 A.0
CPM28:
Devices:
Error in receive frame threshold.
MPC8260, MPC8255 Description: In SCC Rx in HDLC mode RFTHR does not work. There is no way to get interrupt on the receive side after a programmable number of frames. Workaround: RFTHR should be programed to 1. Fix Plan: Fix on HiP3 B.1
CPM29:
Devices:
MAXD1 and MAXD2 may not be less than MFLR.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 30 Freescale Semiconductor
Description: In SCC Rx Ethernet, the option of transferring only part of a frame into memory (MAXD1 and MAXD2 < MFLR) does not work. Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM30:
Devices:
Graceful stop command does not work.
MPC8260, MPC8255 Description: Graceful stop command does not work in SCC Tx in the following protocols: Ethernet, HDLC, Transparent Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM35:
Devices:
Data corruption in SCC transparent mode.
MPC8260, MPC8255 Description: (4350) When using SCC transparent, envelope mode and the received frame size is (4*n) + 1, the last byte is corrupted. When using GSMR_H(RFW) - rx FIFO width, the received data is completely corrupted, not just the last byte. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.1
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 31
CPM36:
Devices:
SI sync timing restriction.
MPC8260, MPC8255 Description: SI's sync signal may not change exactly on clock edge in the following cases. The bug affects operation only when the SI is in one of two modes: 1. sd = 00, ce = 0, fe = 0, dsc=1 -- (Sync sampled with falling edge -> Sync should not change on rising edge) 2. sd = 00, ce = 1, fe = 1, dsc=1 -- (Sync sampled with rising edge -> Sync should not change on falling edge) Workaround: When working in these modes the sync signal to the SI should be manipulated such that it will not change on the exact edge of the serial clock. The errata can be Workaround by toggling the sync at least 5ns after the edge. One way to implement such a workaround is adding a non inverting buffer between the device that generates the sync signal and the XPC8260 that uses it. Fix Plan: Fix on HiP3 B.1
CPM38:
Devices:
Heart beat error and carrier sense lost error on two frames.
MPC8260, MPC8255 Description: There are rare case when heart beat error and carrier sense lost error will be reported on two frames. The error is reported in the frame in which it occurred but in those rare cases it is also reported on an adjacent frame. Workaround: -- Fix Plan: Fix on HiP4 A.0
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 32 Freescale Semiconductor
CPM39:
Devices:
Corruption in AAL0 cell payload.
MPC8260, MPC8255 Description: There is a rare case when using ATM AAL0 transmitter that the AAL0 cell payload may be corrupted. This can occur in certain internal sequence of events that can not be controlled or detected by the user. Workaround: Use the microcode patch available from Freescale. Alternatively when working with AAL0 SAR, place the TCELL_TMP_BASE 64 byte align plus 4. For example use TCELL_TMB_BASE = 0x2d04 not 0x2d00. Fix Plan: Fix on HiP3 B.1
CPM40:
Devices:
Corruption in AAL0 IDLE Cell.
MPC8260, MPC8255 Description: There is a rare case when transmitting ATM idle cell that the idle cell may be corrupted. This can occur in certain internal sequence of events that can not be controlled or detected by the user. Workaround: Place the Idle Base template at address 64 byte align minus 4. For example use Idle_BASE = 0x2cfc not 0x2d00. Fix Plan: Fix on HiP3 B.1
CPM41:
Devices:
Limitation in ATM controller.
MPC8260, MPC8255 Description: There are some limitations in the ATM controller. The first limitation is that only the first 8 PM tables can be used instead of 64. When using these 8 tables, the user must clear the 5 most significant bits of TBD_BASE (in case of Tx PM) or RBD_BASE (in case of Rx PM). The second limitation is that only the first 2048 ATM channel numbers can be used.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 33
Workaround: Use the microcode patch available from Freescale which fixes the performance monitoring limitation problem described above. However the ATM channel number limitation has no workaround. Fix Plan: Fix on HiP3 B.1
CPM42:
Devices:
Data corruption in MCC.
MPC8260, MPC8255 Description: Data corruption may occur in the receive buffers of MCC channels when more then one TDM slot uses 7 bits of contiguous data. Workaround: It is possible to avoid this problem by splitting the 7 bits slots between two SI RAM entries such that one entry will represent 4 bits of the slot and the other SI entry will represent 3 bits of the slot. When initializing the 2 spliced channels, shadow RAM must be used to keep the 2 channels synchronized. This problem occurs only when all the 7 bits are represented by one entry in the SI RAM. Fix Plan: Fix on HiP3 B.1
CPM43:
Devices:
TxCLAV ignored by UTOPIA in single PHY mode.
MPC8260, MPC8255 Description: When the FCC transmitter is configured to work in UTOPIA single PHY master mode, it will ignore negation of the TxCLAV signal. Thus due to this errata the UTOPIA slave will be unable to control the flow of cells by negating TxCLAV. Workaround: Configure the FCC transmitter and receiver to work in multi-PHY master mode by programming FPSMR[TUMP/RUMP] = 1 and limit the number of ATM PHYs to 1 by programming FPSMR[LAST PHY] = 00000. Fix Plan: Fix on HiP3 B.1
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 34 Freescale Semiconductor
CPM44:
Devices:
Zero insertion error on MCC.
MPC8260, MPC8255 Description: When using MCC transmitter in HDLC super channel mode, a zero insertion at the last bit before the flag may fail to occur. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.1
CPM45:
Devices:
Error in CLAV sample point.
MPC8260, MPC8255 Description: In FCC ATM transmit master mode (multiple PHY only), the CLAV signal is sampled 5 clocks before the end of the cell instead of 4 clocks. This is relevant only for back to back transmission sequence. Workaround: In multiple PHY fix priority polling mode, by adding a dummy PHY, it is possible to ensure that the dummy PHY will be polled at payload 44 (5 clocks before the end of the cell). This is possible since the cell length is constant and the number of PHY to poll is also constant. Fix Plan: Fix on HiP3 B.1
CPM46:
Devices:
Error in internal prioritization of CPM resource.
MPC8260, MPC8255 Description: Each of the communication controllers (FCC, MCC, SCC,...) issue request for service to the CPM with different priorities in order to receive the necessary assistance in time. Because of an internal connection
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 35
error, the FCC3 request for service is issued with a much lower priority than intended. Because of this, FCC3 might sporadically over-run when the CPM is heavily loaded. Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM47:
Devices:
Error in tri-state ability of two TxDATA signals using 16-bit UTOPIA interface on FCC1.
MPC8260, MPC8255 Description: Two of the TXDATA signals using the 16 bit UTOPIA bus on FCC1 cannot be tri-stated. The two signals are PD[5] (txdata[3]) and PD[6] (txdata[4]). In a MPHY system were the XPC8260 is configured as a UTOPIA slave, tri-stating of these signals is required when the XPC8260 is not the selected UTOPIA slave or polled device. Additionally the signals PD[11] (TDMB2: L1RQ) and PD[10] (TDMB2: L1CLKO) may be tri-stated sometimes (erroneously) when FCC1 is configured to work in ATM. Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM48:
Devices:
Error in TDM.
MPC8260, MPC8255 Description: Disabling TDMx may interfere with the operation of TDMy in case TDMy uses the SI-RAM blocks directly above those used by TDMx. For example: -- start address of TDMc = 0 -- start address of TDMb = 2 -- start address of TDMa = 4 -- start address of TDMd = 6 -- When disabling TDMa, TDMb will be affected.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 36 Freescale Semiconductor
-- When disabling TDMb, TDMc will be affected. -- When disabling TDMd, TDMa will be affected. -- When disabling TDMc, no TDM will be affected. Workaround: Instead of disabling a TDM, the user can switch to a shadow RAM, which contains only non supported slots in its entries. Fix Plan: Fix on HiP4 A.0
CPM49:
Devices:
Error in FEC CAM address recognition.
MPC8260, MPC8255 Description: External CAM address recognition in fast Ethernet controller, does not function. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.1
CPM50:
Devices:
Error in loss of alignment.
MPC8260, MPC8255 Description: When configuring the MCC to work in Transparent, Super channel First sync slot synchronization, loss of alignment may occur. This will occur when the first data (idles) on the Rx data line matches the value of the RCVSYNC parameter. Workaround: Write to RCVSYNC a pattern that cannot appear in the Rx data line. Fix Plan: Fix on HiP4 A.0
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 37
CPM51:
Devices:
Pointer insertion/extraction error in AAL1 CES.
MPC8260, MPC8255 Description: When a pointer value of 93 need to be inserted/extracted to/from a cell with SN different then 6, the pointer will not be treated correctly. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.3
CPM52:
Devices:
Error in ATM internal rate mode.
MPC8260, MPC8255 Description: ATM internal rate mode underruns can cause the CPM to behave erratically, and possibly to crash. Symptoms are either loss of a transmitted cell, or possibly a CPM crash requiring a CP reset. This only affects systems working in internal rate mode (that is, FTIRRx[TRM] = 1). Systems working in external rate mode will never experience this bug. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.3
CPM53:
Devices:
Inability to run RAM microcode.
MPC8260, MPC8255 Description: Large RAM microcode packages will not run on rev B.1 or B.2 device. This includes AAL2 and the enhanced SS7 microcode packages. Small microcode patches (less than 2Kbytes) for CPM errata fixes are not effected.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 38 Freescale Semiconductor
Workaround: -- Fix Plan: Fix on HiP3 B.3
CPM54:
Devices:
Error in switching to and from shadow SI RAM.
MPC8260, MPC8255 Description: Dynamic switching in SIRAM may not occur properly if the following restrictions are not applied. Workarounds: In SI RAM, when working with shadow RAM, the last entry (n) and the entry immediately before the last entry (n-1) MUST have at least one common bit in the CNT or BYT fields. For Example: * * * * * * * SIRAM Entry n-1 n n-1 n n-1 n CNT FieldByte Field 0001 0101 1010 0010 1000 0010
The above is okay
The above is okay
The above is not okay. Fix Plan: Fix on HiP4 A.0
CPM55:
Devices:
Error in ATM_Transmit command.
MPC8260, MPC8255 Description: The ATM_Transmit command do not execute correctly when used on APC priority above 4.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 39
Workaround: -- Fix Plan: Fix on HiP3 B.3
CPM56:
Devices:
AAL2 microcode in ROM does not function.
MPC8260, MPC8255 Description: Due to a contention on the CPM internal bus the enhanced AAL2 microcode integrated into ROM on Rev B.3 is not functional. Workaround: Use the RAM based Enhanced AAL2 microcode package available from Freescale. Fix Plan: Fix on HiP4 A.0
CPM57:
Devices:
AAL5 cell corruption.
MPC8260, MPC8255 Description: When configured for ATM AAL5 operation, sometimes a small percentage of data packets received are corrupted. The second part of a second ATM cell received is incorrectly DMAed to memory and overwrites the second part of the first ATM cell received in a frame, and the CPM indicates no errors but data in memory is wrong. Note that this data corruption happens only if the AAL5 free buffer pool feature is enabled and the BDs' buffers are on the 60x bus and CTs are on the local bus. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 C.2
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 40 Freescale Semiconductor
CPM62:
Devices:
The CPM PLL does not lock reliably for certain multiplication factors.
MPC8260, MPC8255 Description: If the CPM multiplication factor is 2.5, 3.5, 5 or 6 the internal PLL will not lock reliably, which will result in erratic behavior. Sometimes (mainly at bus frequencies lower than 50 MHz) it might lock, however it might loose the lock after worth. If one of the other multiplication factors (2,3 or 4) is selected, the CPM PLL will lock reliably, even at 66 Mhz bus speed. Workaround: Do not use the non-reliable multiplication factors. For 166 Mhz CPM use 55 Mhz bus frequency and a CPM multiplication factor of 3. Fix Plan: Fix on HiP3 C.2
CPM64:
Devices:
AAL5 RxBD[LNE] error generated if PDU length exceeds 65512 bytes.
MPC8260, MPC8255, MPC8250, MPC8260A, MPC8255A, MPC8264, MPC8265, MPC8266 Description: When the CPM receives an AAL5 PDU between 65512-65535 bytes (maximum length). The CPM sets the RxBD[LNE] indicating a receive length error, however the memory buffer contents for the PDU are correct. Workaround: Use the microcode patch available from Freescale, or, alternatively, receive AAL5 PDU less than 65512 bytes. Fix Plan: Fix on HiP4 B.1
CPM65:
Devices:
SS7 microcode in ROM is not fully functional.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 41
Description: The SS7 microcode in ROM on Rev B.x silicon is not fully functional and should not be used. Please refer to the release note available with the latest SS7 RAM microcode release for Rev B.3 for more details. Workaround: Use the enhanced SS7 microcode package (available for Rev B.3 only). This microcode is not available for Rev B.1 and B.2 silicon due to errata CPM 53. Fix Plan: Fix on HiP3 B.0
CPM71:
Devices:
CPM does not snoop MCC buffer descriptors.
MPC8260, MPC8255 Description: When the MCC performs a DMA read or write of the buffer descriptor, GBL is not asserted and TC2 is always driven low. Therefore cache snooping will not be enabled for MCC BDs, therefore BDs in memory will not match the data cache. Also the bus used for the DMA is always the 60x, therefore if the BDs are on the local bus then the DMA consumes bandwidth on both the 60x and Local bus. Workaround: If GBL and/or TC2 are set in the MCC TSTATE/RSTATE parameters. Use the microcode patch available from Freescale. If GBL and TC2 are not set to improve performance move the MCC BDs to the 60x bus. The microcode patch will fix both the GBL/TC2 and the bus performance issue. Fix Plan: Fix on HiP3 C.2
CPM72:
Devices:
MCC global underruns.
MPC8260, MPC8255 Description: There is a rare case when MCC transmitter global underrun (GUN) errors may occur during intensive CPM activity even when estimated CPM bandwidth is less than 100%. This is due to the prioritization of the MCC transmitter relative to other CPM resources. In Rev C.2 silicon and forward a new feature has been added to the 8260, which will allow users to condition the MCC transmitter priority mechanism and remove expected MCC GUNs errors without effecting the performance of other peripherals in the CPM. This feature will controlled by a new MCC
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 42 Freescale Semiconductor
mode bit in the RCCR, which will allow users to continue to use the current CPM priority scheme in their applications if required. Please refer to the MPC8260 PowerQUICC IITM Family Reference Manual for more details. Workaround: -- Fix Plan: Fix on HiP3 C.2
CPM73:
Devices:
SIRAM corruption.
MPC8260, MPC8255 Description: An access to the SI RAM bank from the 60x bus while the corresponding TDM is active may result in data corruption within the SI RAM. Workaround: Associate the SI RAM bank with an inactive TDM before attempting to access it. Once the accesses has been made, the SI RAM bank should be re-assigned to the active TDM. Fix Plan: Fix on HiP3 C.2
CPM75:
Devices:
AAL2 microcode in ROM is not fully functional.
MPC8260, MPC8255, MPC8250, MPC8260A, MPC8255A, MPC8264, MPC8265, MPC8266 Description: The enhanced AAL2 microcode integrated into ROM on Rev C.2 is not fully functional. Workaround: Use the RAM-based enhanced AAL2 microcode package available from Freescale. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 43
CPM77:
Devices:
TC layer transmits and receives data LSB first instead of MSB first.
MPC8264, MPC8266 Description: The internal TC layer hardware is connected to the UTOPIA data bus in the reverse order. This means the transmitter transmits the data LSB first and not MSB first as required. The HEC will be generated according to the reversed data. On the receive side data will be received in the right order, the HEC will be checked correctly but the data will be delivered to the UTOPIA Rx data bus in the reverse order. Workaround: Use the MPC8260 TC layer in internal loopback mode for development purposes. Fix Plan: Fix on HiP4 B.1
CPM78:
Devices:
IMA microcode in ROM is not fully functional.
MPC8264, MPC8266 Description: The IMA microcode integrated into ROM is not fully functional. Refer to latest IMA RAM microcode release for more details. Workaround: Use the IMA RAM microcode package available from Freescale Fix Plan: No fix plan at this time.
CPM79:
Devices:
FCC Fast Ethernet flow control.
MPC8260, MPC8255 Description: When the FCC receives a flow control pause message with MAC parameter = 0xffff, it sets a zero delay instead of maximum delay.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 44 Freescale Semiconductor
Workaround: -- Fix Plan: Fix on HiP3 B.1
CPM80:
Devices:
MCC CES user template.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: If the transparent MCC Tx CES channel requires the user template (CHAMR[UTM] = 1) then only the first 8 bytes of the user defined pattern are transmitted. Then the transmitter will continue to send bytes 4-7 of the pattern continuously until the counter reaches 0. Any bytes defined in the pattern after byte 7 are never transmitted. Workaround: Use a template size of 8 bytes. Fix Plan: Fix on HiP4 B.1
CPM81:
Devices:
Japanese SS7 error interval timer problem.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: The Japanese error interval for the SS7 code is not timed correctly. The error interval timer is started on the reception of every SU, it should be running in the background and expiring on a user programmable time of every N*512us (where 0<=N<=65535). This problem only affects the SS7 microcode in Japanese mode. Workaround: Use the RAM based SS7 microcode package available from Freescale. Fix Plan: Fix on HiP4 B.1
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 45
CPM85:
Devices:
AAL0 only one BSY interrupt generated.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When using AAL0, only one BSY interrupt will be received regardless of the number of BSY events that are generated. Workaround: -- Fix Plan: Fix on HiP4 B.1
CPM86:
Devices:
Random PHY number for FCC Rx in Single-PHY master mode.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When FCC Receive ATM controller is configured for Single PHY Master mode (FPSMR[RUMP] = 0, FPSMR[RUMS] = 0) and FPSMR [LAST PHY / PHY ID] is not equal to zero, a random PHY ID might be allocated to the incoming cells instead of the expected zero (for Single-PHY).This will result in a loss of cells. This configuration is typical when using the FCC Transmit ATM controller in Multi-PHY Master mode together with the FCC Receive ATM controller in Single PHY Master mode. Workaround: The Address Lookup Mechanism should be created in such a way that for any PHY address input, the output will be as for PHY 0. Fix Plan: Fix on HiP4 B.1
CPM88:
Devices:
MCC transmit GUN when `MCC STOP RX' CPCR command is used.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 46 Freescale Semiconductor
Description: An MCC may experience a highly intermittent transmit GUN event indication, related to MCC receive channels that have been stopped through the `MCC STOP RX' host CPCR command. This GUN can happen unrelated to internal CPM loading or other external factors. Workaround: Avoid using `MCC STOP RX' command using one of the following mechanisms -- Simply stop the TDM -- Use shadow RAM and dynamically remove the desired MCC RX channel entry from SIRAM programming (see Chapter 14 of the MPC8260UM). To use the second mechanism, the following procedure should be utilized, using an extra redundant shadow RAM switch. This is done to provide a full TDM frame's amount of time to ensure receive activity is complete and will avoid the issue: a) Re-program shadow SIRAM to remove channel to be stopped b) Switch to shadow SIRAM and wait for that TDM's bit in the SIxSTR register to change to indicate switch complete c) Copy this new shadow RAM programming back to the main SIRAM bank d) Switch to active RAM, again wait for switch to complete Then software can re-initialize or modify the removed channel's RX parameters Fix Plan: Fix on HiP4 B.1
CPM92:
Devices:
TC Layer when disabled can be selected by FCC2.
MPC8264, MPC8266 Description: When the TC layer is enabled for transmit or receive (TCMODEx[TXEN/RXEN] = 1) and transmits or receives an ATM cell (by asserting TxClav or RxClav). The FCC continues to poll the CLAV signal and will respond to a disabled TC layer before it moves to the next TC layer (enabled or disabled). This will have an impact on the ATM CPM performance. Workarounds: 1. Use sequential TC Layers (TCMODEx[TXEN], [RXEN] = 1) from TC Layer number 1 to TC Layer number n and program FPSMR[LastPHY] = n-1. 2. For transmit program the disabled TC layer to transmit idle by preparing the APC parameter table, priority-level tables for the corresponding PHY with CPS = 0 and no channel scheduled. For receive, if the user is working with CAM, set the MS bit (MS = 1:not match) of the entries correspondent to the disabled TCs. If the user is working with Address Compression, program the VP_MASK and the VCOFFSET so the cells coming from the disabled PHYs will get an MS = 1.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 47
Fix Plan: No fix plan at this time.
CPM93:
Devices:
IDMA microcode in ROM is not fully functional.
MPC8260, MPC8255 Description: The IDMA microcode integrated into ROM on Rev A.1 is not fully functional. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP3 B.1
CPM94:
Devices:
FCC RTS signal not asserted correctly.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: At the beginning of an HDLC frame transmission that is preceded by more than one opening flags, RTS will not be asserted if CTS is negated. This may cause a deadlock if the modem waits for the assertion of RTS before asserting CTS. Workarounds: -- Transmit no flags between or before frames. Clear FPSMR[NOF] bit. -- Set GFMR[RTSM] = 1 to ensure RTS/ is asserted when FCC is enabled. However no hand shaking activities with the modem will occur for all the proceeding frames. Fix Plan: No fix plan at this time.
CPM95:
Devices:
ATM false indication of miss inserted cells.
MPC8260, MPC8255
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 48 Freescale Semiconductor
Description: There is a false indication of unassigned bits in the PHY:VPI:VCI, which could cause ATM cells to be treated as miss-inserted cells and therefore discarded. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP4 A.0
CPM96:
Devices:
ATM performance monitoring with AAL1 CES.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: Data in DPRAM is corrupted when performance monitoring is enabled in the receiver. Workarounds: -- Disable Receive Performance Monitoring RCT[PMT] = 0 -- Use the microcode patch available from Freescale Fix Plan: No fix plan at this time.
CPM97:
Devices:
MCC SS7--No SUERM interrupt generated after an ABORT.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: After an ABORT Octet Count Mode is not entered properly when idles are received. Therefore N_Cnt is not decremented and no SUERM interrupt will be generated. This problem only affects the SS7 microcode in ITU-T / ANSI mode (SS7_OPT[STD] = 0). Workaround: Use the latest RAM based SS7 microcode package available from Freescale. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 49
CPM98:
Devices:
I2C erratic behavior can occur if extra clock pulse is detected on SCL.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: The I2C controller has an internal counter that counts the number of bits sent. This counter is reset when the I2C controller detects a START condition. When an extra SCL clock pulse is inserted in between transactions (before START and after STOP conditions), the internal counter may not get reset correctly. This could generate partial frames (less than 8 bits) in the next transaction. Workaround: Do not generate extra SCL pulses on the I2C bus. In a noisy environment the digital filter I2MOD[FLT] and additional filtering capacitors should be used on SCL to eliminate clock spikes that may be misinterpreted as clock pulses. Fix Plan: No fix plan at this time.
CPM99:
Devices:
ABR TCTE[ER-TA] corruption.
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When using the AAL5 ABR ROM microcode it is possible for the TCTE[ER-TA] field to be overwritten with an erroneous value. This, in turn, will cause the TCTE[ER-BRM] to be updated with this value. As TCTE[ER-BRM] holds the maximum explicit rate value allowed for B-RM cells an erroneous value in this field could have a detrimental effect on the network performance. Workaround: Use the microcode patch available from Freescale. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 50 Freescale Semiconductor
CPM100:
Devices:
ABR TCTE address miscalculation.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When using the AAL5 ABR ROM microcode with external ATM channels it is possible for the EXT_TCTE_BASE word value (written by the user to DPRAM) to be misread. In this case calculations performed by the microcode to access the users programmed external TCTE will be incorrect with a high chance of the access resulting in a CPM crash. Workaround: Use the microcode patch available from Freescale. Fix Plan: Fix on HiP4 B.1
CPM101:
Devices:
FCC RxClav timing violation (slave).
MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: FCC ATM Receive UTOPIA slave mode. When the RxFIFO is full, RxClav is negated 2 cycles before the end of the cell transfer instead of 4. A master that polls RxClav or pauses 3 or 4 cycles before the end of the cell transfer may sample a false RxClav and an overrun condition may occur. The dashed line in the timing diagram below depicts the actual RxClav negation (two cycles before the end of the cell transfer instead of four cycles). The signals in the timing diagram are with respect to the master hence Tx interface is shown. Workarounds: 1. Master should not poll RxClav or pause cell transfer at 4 cycles before the end of cell transfer. Master should poll 2 cycles before the end of the current cell or later. This can be achieved by introducing a cell-to-cell polling (and transfer) delay, which is equal or larger then one cell transfer time. If this can be achieved, the impact on performance is minimal. 2. Configuring ATM only on FCC1 and setting FPSMR[TPRI] ensures highest priority to FCC1 Rx. In addition, for CPM utilization lower then 80% (as reported by the CPM performance tool based on UTOPIA maximal bus rate) the CPM performance is enough to guarantee that the RxFIFO does not fill up.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 51
TxClk TxEnb
TxClav
TxData
TxSOC
Figure 1. Transmit Timing for Cell-Level Handshake
-- Multi-PHY with single Clav polling--Master should ensure that the address corresponding to an MPC826xA slave is not placed on the address bus before 5 cycles before the end of a cell transfer to that slave. Fix Plan: No fix plan at this time.
CPM110:
Devices:
FCC1 prioritization.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: FCC1 receiver in Ethernet, HDLC or Transparent controller mode is not elevated to emergency status (priority 4 in Table 14-2, "Peripheral Prioritization," in the MPC8260 PowerQUICC II Family Reference Manual), which may lead to FIFO overrun if the system is heavily loaded (FCC1 receiver has the highest priority excluding emergency status of other peripherals). Workarounds: 1. When allocating FCCs, assign FCC2 and/or FCC3 for Ethernet, HDLC or transparent before FCC1, or assign FCC1 to the lowest bit rate interface. If FCC1 is allocated for ATM and requires higher CPM utilization then the other FCCs, disable its emergency status. 2. If FCC1 is allocated for Ethernet or HDLC and FCC2 for ATM, disable emergency status of FCC2 by setting FPSMR[TPRI].
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 52 Freescale Semiconductor
Fix Plan: No fix plan at this time.
CPM111:
Devices:
FCC missing reset at overrun.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: Overrun error condition does not reset the FCC receiver in Ethernet mode, and may not set OV status in the RxBD. If RMON is not set frames may be received with CR status continuously. CR and LG status or JBRC counts might be due to overrun condition. Fragment of a later frame may be appended to a fragment of an earlier one. If this frame length exceed MFLR, it will be discarded without indication on the RxBD. RMON JBRC will be incremented (false jabber). Workaround: Use the microcode patch provided by Freescale. Fix Plan: No fix plan at this time.
CPM112:
Devices:
FCC missing status.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: TxBD may not be closed for FCC in Half duplex 10BaseT Ethernet. There might become a mismatch between the actual transmitted BD and the BD for which status is updated. As a result, the status of one to three BDs may not be updated, and they would appear "Ready", although the associated frames have been transmitted (assuming a frame per BD). Workaround: Use the microcode patch provided by Freescale. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 53
CPM113:
Devices:
Incorrect return value from event register read (SCC, SPI, I2C, and SMC).
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: Under specific conditions, the value returned from an event register (SCC, SPI, I2C, SMC) read might be zero, although some event bits are actually set. If the read operation is done as part of the interrupt handling routine, and no action is taken due to the zero value, the interrupt handler will be invoked again since the pending register bit will still be set. The subsequent read will most probably return the correct value. This should not cause any issue other than some minor performance impact. This issue exists only in the SCC, SMC, I2C and SPI. Workarounds: -- Fix Plan: No fix plan at this time.
CPM114:
Devices:
IDMA transfer has an extra DACKx.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: In rare cases certain systems that use DREQ level-sensitive mode may show an additional DACKx cycle after DREQ has ben deactivated. This causes extra data to be sent. When the following conditions are all true: -- the CPM IDMA operates in external request mode -- the DREQ signal is set to be level-sensitive -- the IDMA is writing to an external peripheral the CPM may sample DREQ too early and thus erroneously start another DTS byte transfer sequence. This erratum is resolved by a microcode patch. The effect of the patch is to have the IDMA perform a read bus transaction at the end of every DTS byte transfer sequence. DREQ is not sampled until this read completes. The address of the read must be on the same bus as the external peripheral. Please refer to the README file of the CPM114 microcode patch for more details. Workaround: Use DREQ edge-sensitive mode.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 54 Freescale Semiconductor
Fix Plan: Use the microcode patch provided by Freescale.
CPM115:
Devices:
APC transmits unwanted idle cells.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: In heavily loaded ATM applications, if the ATM pace controller (APC) is configured for multiple priority levels and a burst of traffic for transmission is sustained for a long enough on the highest priority APC table, then unwanted idle cell could be transmitted on the lower priority APC tables when there are cells available in lower priority APC scheduling table for transmission. The transmission of the unwanted idles could cause the valid ATM cells on lower priority APC scheduling tables not to be transmitted. This could affect all ATM channels that are not located in highest priority APC scheduling table. Workaround: Increase the size of lower priority APC scheduling tables so they are large enough to absorb any burst or back-to-back bursts on the highest priority APC scheduling table. Or use the microcode patch available from Freescale. Fix Plan: No fix plan at this time.
CPM116:
Devices:
The pointer value of 93 is not supported in PFM mode of AAL1 CES.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When working in PFM mode (Partially Filled Mode), the pointer value of 93 is not generated. It causes the loss of synchronization at the far end. Also when receiving the pointer value of 93, the synchronization will be lost, which causes loss of data and resynchronization routine. Workaround: Use the microcode patch available from Freescale. Fix Plan: No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 55
CPM117: False address compression.
Devices: MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: If there are active AAL0 channels and a CRC-10 error has been received, VP-level address compression might have false results, which could lead to one of the following: - Wrong calculation of a VP pointer address - Cells might be falsely discarded as misinserted cells - Misidentification of misinserted cells (in CUAB mode) This is a statistical error, which is conditional on the reception of AAL0 cells with CRC-10 error. The probability of false address compression is directly correlated with higher CPM bit rate and longer system bus latency. Note: While the false address compression is possible only if there are active AAL0 channels, it might impact all AAL types. However, it cannot occur unless AAL0 cells with CRC-10 error have been received beforehand. Workaround Use microcode RAM patch provided by Freescale. Fix Plan No fix plan at this time.
CPM118: MCC Rx, Aborted HDLC frames.
Devices: MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When an aborted HDLC frame is followed by a good frame, there may appear in the receive data buffer both the data of the aborted frame followed by the data of the good frame. Workaround Use microcode RAM patch provided by Freescale. Fix Plan Next revision.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 56 Freescale Semiconductor
CPM119: FCC Tx, Incorrect handling of ethernet collision.
Devices: MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: When an ethernet collision occurs on the line 125 clocks after Tx-En assertion, late collision will be reported even though this is only 63 bytes into the frame instead of 64. When a collision occurs 124 cycles after Tx_En assertion, no event is reported, the TxBD is not closed, and transmission halts. Retransmission behavior is correct for collisions occurring between assertion of Tx_En and 123 clocks. Workaround Use microcode RAM patch provided by Freescale. Fix Plan Next revision.
CPM120:
Devices:
SS7_OPT[FISU_PAD] parameter has no effect on the number of flags between FISUs.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266 Description: The SS7_OPT[FISU_PAD] parameter has no effect on the number of flags between FISUs. Regardless of the value of this field, one flag will be present between back-to-back FISUs. Workaround Use the latest SS7 microcode package provided by Freescale. Fix Plan No fix plan at this time.
CPM121:
Devices:
Data frame may be corrupted if writing to xMR registers while other TDM channels are active.
MPC8260, MPC8255, MPC8260A, MPC8255A, MPC8250, MPC8264, MPC8265, MPC8266
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 57
Description: The issue is data corruption in a working TDM during the enabling/disabling of the second TDM in the System. When writing to one of the following SI registers--GMR, AMR, BMR, CMR, DMR--while one or more TDMs are working, one data frame of a working TDM might get corrupted. Workaround It is recommended to work with the shadow RAM when wanting to change data and not to disable and then enable the TDM. Fix Plan No fix plan at this time.
MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 58 Freescale Semiconductor
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MPC8260 PowerQUICC IITM Family Device Errata, Rev. 4.6 Freescale Semiconductor 59
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MPC8260CE Rev. 4.6 11/2004

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